One of the most critical challenges for today’s and future data-intensive and big-data problems (ranging from economics and business activities to public administration, from national security to many scientific research areas) is  data storage and analysis. The primary goal is to increase the understanding of processes by extracting highly useful values hidden in the huge volumes of data. The increase of the data size has already surpassed the capabilities of today’s computation architectures which suffer from the limited bandwidth (due to communication and memory-access bottlenecks), energy inefficiency and limited scalability (due to CMOS technology). This collaboration targets the development, the design and the demonstration of a new architecture paradigm for big data problems; it is based on the integration of the storage and computation  in the same physical location (using a crossbar topology) and the use of non-volatile resistive-switching technology, based on memristors, instead of CMOS technology. Therefore, it will reduce both the memory wall and energy consumption with orders of magnitude. Due to the nature of the architecture, it will support massive parallelism; hence, significantly improving the performance and enabling the solution of big-data problems in minutes or at the most in hours instead of many days.


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